The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Substrate processing systems increasingly need to use high aspect ratio etching when processing features of substrates such as semiconductor wafers. For example, high aspect ratio etching may be used when processing substrates for dynamic random access memory (DRAM). In these applications, very high aspect ratio cylinders are etched in oxide or poly materials.
With technology shrinking in two dimensional (2D) space and moving towards three dimensional (3D) applications, improved methods for etching high aspect ratio features will be needed. Examples of 3D structures include 3D vertical NAND structures with 2D flash devices that are stacked over each other vertically. 3D scaling also requires very high aspect ratio etching. For example, 3D scaling may be used for memory hole etching in 3D vertical NAND flash applications. There are other applications such as cross-point memory structures where high aspect ratio etching of features is also required.
High aspect ratios generally require high ion energy to etch the high aspect ratio features. At high ion bombardment energy levels, mask selectivity is very important. New mask materials that are harder and have very high etch resistance under high ion bombardment energy levels are therefore being considered. Materials being evaluated as masks include metal or metal-based derivatives. These materials are harder to pattern using plasma etching because the hard mask materials do not have substantial volatile etch byproducts.